CAP2FE=DISABLED, CAP2RE=DISABLED, CAP1RE=DISABLED, CAP0FE=DISABLED, CAP1FE=DISABLED, CAP0RE=DISABLED, CAP2I=DISABLED, CAP0I=DISABLED, CAP1I=DISABLED
Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place.
| CAP0RE | Rising edge of capture channel 0: a sequence of 0 then 1 causes CR0 to be loaded with the contents of TC. 0 (DISABLED): Disabled. 1 (ENABLED): Enabled. |
| CAP0FE | Falling edge of capture channel 0:: a sequence of 1 then 0 causes CR0 to be loaded with the contents of TC. 0 (DISABLED): Disabled. 1 (ENABLED): Enabled. |
| CAP0I | Generate interrupt on channel 0 capture event: a CR0 load generates an interrupt. 0 (DISABLED): Disabled. 1 (ENABLED): Enabled. |
| CAP1RE | Rising edge of capture channel 1: a sequence of 0 then 1 causes CR1 to be loaded with the contents of TC. 0 (DISABLED): Disabled. 1 (ENABLED): Enabled. |
| CAP1FE | Falling edge of capture channel 1:: a sequence of 1 then 0 causes CR1 to be loaded with the contents of TC. 0 (DISABLED): Disabled. 1 (ENABLED): Enabled. |
| CAP1I | Generate interrupt on channel 1 capture event: a CR1 load generates an interrupt. 0 (DISABLED): Disabled. 1 (ENABLED): Enabled. |
| CAP2RE | Rising edge of capture channel 2: a sequence of 0 then 1 causes CR2 to be loaded with the contents of TC. 0 (DISABLED): Disabled. 1 (ENABLED): Enabled. |
| CAP2FE | Falling edge of capture channel 2: a sequence of 1 then 0 causes CR2 to be loaded with the contents of TC. 0 (DISABLED): Disabled. 1 (ENABLED): Enabled. |
| CAP2I | Generate interrupt on channel 2 capture event: a CR2 load generates an interrupt. 0 (DISABLED): Disabled. 1 (ENABLED): Enabled. |
| RESERVED | Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. |